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SystemVerilog jobs at Aurexis Tech in Singapore

Actively hiring 7 SystemVerilog jobs

7 SystemVerilog jobs at Aurexis Tech in Singapore.

7 live jobs ↑40% 19d
IC Engineer (Design Verification)
Disclosed salary
S$4.5k–6k/mo
Low competition
Senior/ IC Design Engineer (Physical Design)
Disclosed salary
S$5k–10k/mo
Normal competition
Senior/ IC Design Engineer (Physical Design)
Disclosed salary
S$5k–10k/mo
Low competition
Senior/ IC Design Engineer (Design Verification)
Disclosed salary
S$5k–10k/mo
Low competition
Senior/ IC Design Engineer (Design Verification)
Disclosed salary
S$5k–10k/mo
Low competition
Senior/ IC Design Engineer (Design Verification)
Disclosed salary
S$5k–10k/mo
Low competition
Senior/ IC Design Engineer (Design Verification)
Disclosed salary
S$5k–10k/mo
Low competition