SG

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UVM jobs at Silicon Labs in Singapore

Actively hiring 5 UVM jobs

5 live jobs 28d

Design Verification Engineer II

Estimated salary

~S$7.5k–9.5k/mo

High competition

Senior Staff/ Staff Design Engineer

Estimated salary

~S$7k–10.5k/mo

Normal competition

IC Design Engineer

Estimated salary

Very high competition

Design Verification Engineer II

Estimated salary

~S$7.5k–9.5k/mo

High competition

Senior Staff/ Staff Design Engineer

Estimated salary

~S$7k–10.5k/mo

Very high competition

Other skills Silicon Labs looks for

RF 17 Python programming 12 Python 9 NPI 8 RTL Design 8 Root Cause Analysis 8 RTL Coding 8 SAP 7 Test 6 ATE 6 SQL 6 Data Analysis 6 ASIC 5 Energy Management 5 Advanced Planning & Scheduling (APS) 5 Scripting 5

About Silicon Labs

Silicon Labs is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers with the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets.

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