Responsibilities
Support the maintenance of the Design and Verification environment, including upkeep of test regression suites. Assist with test case preparation, log analysis, and bug triaging. Contribute to design documentation by writing clear technical notes, updating block diagrams, and maintaining internal wikis.
Assist in running PPA (Performance / Power / Area) analysis tools and interpreting results alongside the design team. Support the team in performance modelling and data transaction analysis, gaining hands-on exposure to NPU throughput concepts. Develop familiarity with the mathematics of convolution operators and arithmetic formats (fixed-point and floating-point).
Requirements
Pursuing a degree in Electrical Engineering, Computer Engineering, or a related field (final year or pre-final year preferred). Basic coursework or project exposure to digital logic design and HDL (Verilog / SystemVerilog). Foundational understanding of convolution operations and number representations (fixed-point and floating-point), whether from coursework or self-study.
Familiarity with programming in Python, C, Verilog, or SystemVerilog; experience in a Linux development environment is a plus. Exposure to deep learning concepts such as CNNs or Transformer architectures, through coursework or personal projects, is a plus. Prior project or lab experience with FPGA or ASIC design flows is a plus.
Detail-oriented, eager to learn, and able to work effectively in a collaborative team environment. Strong written and verbal communication skills for documentation and cross-functional interaction.