Design Verification Engineer jobs in Singapore with the fewest applicants
37 live jobs
Design Verification Engineer jobs across Singapore, paying a median of S$7,500/mo, typically between S$6,888 and S$9,375. The skills most in demand are UVM, SystemVerilog, Functional Coverage and C++.
37 live jobs ↑9% 15d17 companies
(Staff/Sr. Staff) Digital Design Verification Engineer
Omnivision1 Venture Avenue
Disclosed salary
S$7k–14k/mo
Low competition
(Sr./Staff) Digital Design Verification Engineer
Omnivision1 Venture Avenue
Disclosed salary
S$5.5k–11k/mo
Low competition
Design Verification Manager
Omnivision1 Venture Avenue
Disclosed salary
S$9k–18k/mo
Normal competition
S
Senior Engineer, Digital IC Verification
STMicroelectronics
Estimated salary
~S$7.5k–9.5k/mo
Low competition
Senior/ IC Design Engineer (Design Verification)
Aurexis Tech
Disclosed salary
S$5k–10k/mo
Low competition
Senior/ IC Design Engineer (Design Verification)
Aurexis Tech
Disclosed salary
S$5k–10k/mo
Low competition
Senior/ IC Design Engineer (Design Verification)
Aurexis Tech
Disclosed salary
S$5k–10k/mo
Low competition
M
Senior Engineer, STPG PE (FDV-Verilog)
Micron Technology990 Bendemeer Road
Estimated salary
~S$5.5k–7.5k/mo
Low competition
Security Systems Verification Engineer
Henderson Security Services601 Macpherson Road
Disclosed salary
S$4k–7k/mo
Low competition
A
Staff Engineer - Design Verification
Ambiq16 Raffles Quay
Disclosed salary
S$10k–15k/mo
Normal competition
Design Verification Engineer
Black Sesame Technologies1 Fusionopolis Walk
Disclosed salary
S$6k–9k/mo
Normal competition
Digital Engineer
Silicon Labs18 Tai Seng Street
Estimated salary
~S$5.5k–10k/mo
Normal competition
Digital Verification Engineer
Analog Devices164 Kallang Way
Estimated salary
~S$5.5k–10k/mo
Normal competition